Hypertransport - controller/protocol for interconnecting CPUs and/or various
bus controllers, (designed to support PCI with minimal overhead) at very 
high speeds.

 Check out https://www.hardwaresecrets.com/everything-you-need-to-know-about-the-hypertransport-bus/4/

Currently, versions 1.x, 2.0, 3.0, 3.1

Clock Speeds of 200 MHz to 3.2 GHz (version dependent)

Uses DDR - transfers on up and down tick of clock.

Establishes non-shared point to point interface (link) between each individual
  device and host bridge/controller.

But also allows device to provide tunneling or bridging circuitry as a 
 way to physically link other devices to host.

Maintains pair of unidirectional link for each device, separate link in 
each direction.

Speeds often specified in Transfers, because bus is a variable width 
  parallel bus structure. Not serial.

And packet driven nature of communication means only a portion of the
  bits transferred is 'user data'.

Uses parallel point to point interface between host bridge and target.
  Referred to as links.
  An interface can have 2,4,8,16, or 32 bit links.
     # 32-bit links not implemented on AMD CPUs.
    Minimum width of a link is 2 bits, Not serial.

    For links less than 8 bits,
      bytes are serially distributed across links (little-endian(?)).

    For links greater than 8 bits,
      bytes are distributed round robin between links.

    Point to point interface consists of a unidirectional link in each 
      direction. 
  
    But width of a link in either direction does not need to match.
 
  Uses a version of LVDS for signaling for CAD, CTL, and CLK.

Protocol supports tunnels and bridges.

  Tunnels are circuits that allow a link to physically pass through
    another device with minimal interaction.

  Bridges are routing interfaces that support a tree topology.

  Bridges and tunnels are simplified routers with some buffering capability.

Packet based communication.

   Packet minimum of 4-byte word up to 64 words in size. 

   Must be multiples of 4-byte word.

Uses an additional CTL signal set to distinguish (request, response, or other
  control) packets from data packets. (LVDS)

Transaction based.
  Initialed by a request command/control packet.
    Posted commands do not require a response.
    Non-posted commands expect a "Target Done" packet at end of transaction.

  If command is read,
    expects data packet of up to 64 bytes from target.

  If command is write,
    it transmits a packet of data up to 64 bytes.

    Other Control packets may be inserted between the transfer request 
      packet and the data packet.
      But these control packets may not have associated data with them.

  Maximum data payload of a packet is 64 bytes.

  For unposted, a "target done" must first be generated before next transfer.

  For posted transfer, a new control/command packet followed by a data 
    transfer packet.

  A message (data transfer) larger than 64 bytes is implemented by multiple 
    transactions.

  End points of a link also contain data buffers which is established at 
    configuration time. 

  A device/tunnel/bridge will not forward a packet unless it knows the receiver
    can accept it, thus avoiding failed delivery. (No waits or retries). 
 
Design provides a source clock line for each 8-bit bus width. (LVDS)

All transactions pass through host bridge, even peer to peer transactions.

Uses combination of hardware and software 'link' negotiation to arrive at
an optimal link configuration. Assumes 8-bit link initially.

Similar process for negotiating optimal clock speed. Assumes 200 MHz initially.

Uses PCI style auto-negotiation for discovering interfaced targets. 

Because target, host bridge interface is point to point, Hypertransport
level arbitration meaningless. 

   If target is PCI or other bus controller, it may perform arbitration
     among attached devices.

Supports message driven interrupts (no hardware pins).
  Provides an Interrupt request message packet 
    and an End of interrupt message packet.

  Availability and configuration part of target discovery phase.

  Up to device to use.


Hypertransport 3.0 implements scrambling in data transmission and uses
  different scrambling algorithms for CTL and CAD links.

3.0 also support optional 8b10b encoding